1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same. More particularly, the present invention relates to a flash memory cell and a method for fabricating the same.
2. Description of the Related Art
Flash memory devices are widely adopted in personal computers and electronic apparatuses, since they can be written, read and erased many times and are capable of retaining data when disconnected from electric power.
A typical flash memory cell has a stack-gate structure, which includes a floating gate and a control gate both made from doped polysilicon. The floating gate is disposed between the control gate and the substrate, and is floated without connecting to any circuit. The control gate is electrically connected to a word line. In addition, a tunnel oxide layer is disposed between the substrate and the floating gate, and an inter-gate dielectric layer is disposed between the floating gate and the control gate.
The operating voltage of a flash memory cell is inversely proportional to the gate coupling ratio (GCR) thereof, which is defined as the ratio of the capacitance between the control gate and the floating gate to the total capacitance of the cell. Therefore, increasing the capacitance between the two gates or decreasing the capacitance between the floating gate and the substrate lowers the operating voltage, while an increase in the capacitance between the two gates is generally achieved by increasing the area between the two gates. However, since the cell size is continuously reduced for upgrading the device integration, it is not easy to increase the area between the control gate and the floating gate and thereby raise the gate coupling ratio (GCR) of the cell.